RoboCup: Redesign 2014-2015

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Phase I: Techanical Analysis

The first stage of the 2014-2015 RoboCup redesign involves brainstorming potential upgrades by researching new technologies/resources since the last revision. A parallel analysis of current robot bugs and potential enhancements is also done at this time. Outlined below is a listing of resources that the team used in this brainstorming stage.

Competition 2014 documentation

Team Description Papers (TDP)

Electrical Board Error Logs

Past Electrical Designs

Phase II: Design

During the design phase, specifications are determined for each section of the robot. Experimental results are documented here from all quantitative findings. This phase is also where the high-level ideas from Phase I are tracked to ensure completion.

Logical Controlling Unit

mbed Debugging

To Do

  • Successfully communicate over SPI with a current FPGA and mbed

Completed

  • Build development board for testing FPGA configuration from mbed's flash storage
    • Tested and confirmed working
  • Obtain mbeds for robot use
    • How: 15 mbeds donated by ECE department

Mechanical/Electrical Integration

Max PCB Dimensions

To Do

  • Determine location and placement for dribbler motor header
  • Determine optimal placement direction for drive motor's phase connections (motor board)
  • Add connection header for ball sensor to control board
  • Add wires among connections in CAD assembly files
  • Test motor wire modifications before working on the entire batch of motors
  • Determine kicker connections and integration
  • Determine options using quarter-turn screws for electrical board attachment

Completed

  • Update hall connection header to right angled one
  • Add pin locations to all connection housings in CAD part files
  • Update the 14-pin connection header (female) for the control-to-motor board connection
  • Finalize method for adjusting motor wire lengths when motors arrive
    • Decision: Unsolder from motor's PCB, trim to length, and resolder to motor's PCB
    • Reason: Did not want to delay ordering motors any futher & hand soldering results in higher yields compared against hand crimping
  • Determine placement of battery location

Radio

CC1101 C++ library

nRF24L01+ C++ library

Current protocol [LINK TO BE CREATED & UPDATED]

To Do

  • Determine optimal secondary frequency for base station updates
  • Test methods using breakout boards and compare data rates
  • Successfully communicate using two (2) nRF24L01+ transceivers and two (2) mbeds
  • Research and determine best steps for structuring radio protocol with primary and seconday frequencies
    • The Crazyflie project has basic radio documentation for how they implemented real-time communication with room for expansion
  • Test packet optimizations - Nanopb is promosing for this

Completed

  • Research integration options of the CC1111 and nRF24LU1+
    • Decision: Do not use SoC parts for the base station
    • Reason: Keep radio software on the mbed platform's C++ libraries (SoC would require additional C code for the base station)
  • Order five (5) CC1111 transceivers from TI
  • Successfully communicate using two (2) CC1101 transceivers and two (2) mbeds
  • Obtain breakout boards for CC1101
    • How: Added SMA antenna connector to breakout boards from 2008 fleet
  • Obtain breakout boards for nRF24L01+
    • How: eBay

FPGA

A few major change to the FPGA's Verilog code must be made for the 2015 redesign.

Setting up a computer for Verilog development

  1. Create an account on Xilinx's website
  2. The Xilinx program is called ISE Design Suite (this is on ECE's virtual lab pool computers - can connect to it from anywhere).
    • The desired download link is found under the ISE Design Suite heading
    • The current version at the time of this writing is 14.7 (size: ~6GB)
    • The ISE Design Suite is no longer supported
    • The newer version of Xilinx's software is called Vivado Design Tools, but it does not support the Spartan-3E FPGA
  3. Install the program to your computer
    • The installer will prompt you to select an edition to install
      • Select ISE WebPACK
  4. Obtain a license at the Xilinx page for license management
    • Open the link sent to you after requesting a license
    • Navigate to the Manage Licenses tab
    • Download the license called ISE WebPACK License
  5. Save the downloaded license file to the ~/.Xilinx directory of your computer
    • The program will require you to locate the license's path at first startup

Mandatory user-provided files for Verilog synthesis

  • Verilog files(s)
    • Defines the HDL implementation
    • File Extension: .v
  • Xilinx Constraint File
    • Defines parameters for correct synthesis to the hardware (pin mappings)
    • File Extension: .ucf

FPGA Commands

Command Read/Write Definition
0x00 Read Only Receive Data Readings
0x01 Read/Write Set motor speeds

Example SPI Transfer (0x00 Read)

Array Index Bit(s) Definition
0 7..0 FPGA Version (0x04 in 2014)
1 7..0 Encoder 1 Count (LSB)
2 7..0
 Encoder 1 Count (MSB)
3 7..0
 Encoder 2 Count (LSB)
4 7..0
 Encoder 2 Count (MSB)
5 7..0
 Encoder 3 Count (LSB)
6 7..0
 Encoder 3 Count (MSB)
7 7..0
 Encoder 4 Count (LSB)
8 7..0
 Encoder 4 Count (MSB)
9 7..0
 Motor Fault
10 7..0
 Kicker Status
11 7..0
 Kicker Voltage
12 7..0
 Hall Count 1
13 7..0
 Hall Count 2
14 7..0
 Hall Count 3
15 7..0 Hall Count 4
16 7..0
 Hall Count 5

Example SPI Transfer (0x01 Write)

Array Index Bit(s) Definition
0 7..0 Packet Type (0x01)
1 7..0 Motor 1 Speed (LSB)
2 7..4

Reserved (Always 0x00)

3..2 Motor 1 Drive Mode
1..0 Motor 1 Speed (MSB)
3 7..0 Motor 2 Speed (LSB)
4 7..4 Reserved (Always 0x00)>br/>
3..2 Motor 2 Drive Mode
1..0 Motor 2 Speed (MSB)
5 7..0 Motor 3 Speed (LSB)
6 7..4 Reserved (Always 0x00)
3..2 Motor 3 Drive Mode
1..0 Motor 3 Speed (MSB)
7 7..0 Motor 4 Speed (LSB)
8 7..4 Reserved (Always 0x00)
3..2 Motor 4 Drive Mode
0..1 Motor 4 Speed (MSB)
9 7..0 Dribbler Motor Speed (LSB)
10 7 Kicker Charge
6 Chipper Enable (1=Chip, 0=Kick)
5..4 Reserved (Always 0)
3..2 Dribbler Motor Drive Mode
1..0 Dribbler Motor Speed (MSB)
11 7..0 Kicker Power (<, oxFF=6ms)

Required Pins

  • MOSI
  • MISO
  • SCK
  • nCS
  • PROG_B

To Do

  • Transition the I2C bus lines to the microcontroller
  • Update Verilog for new differential encoder signals (A+, A-, B+, B-)
    • ( (A+) + (A-) == 0 ) should be true for no errors
  • Update Verilog for driving a bootstrap circuit
  • Add a writable register for enabling/disabling motor encoders

Completed

  • Determine required pins for connecting FPGA
  • Document steps for synthesizing Verilog files
  • Successfully configured an FPGA from the mbed's on board flash storage
  • Successfully synthesized a Hello World Verilog file using Xilinx's ISE Webtools
  • Determine what communications occur over the SPI bus
    • Documented in the tables above
  • Finalized that the 2015 motors will use the current FPGA
    • Decision: Xilinx Spartan-3E
    • Reason: FPGA is only used for motor control & no futher capabilities are needed

Motors

Maxon 50W Custom Motor Drawing

Maxon 50W Motor Datasheet

To Do

Completed

  • Order 3 DRV8301 Pre-Drivers from TI
  • Finalize the protyping designs of single motor controllers
  • Order motors

Motion Sensing & Motion Control

MPU-9250 C++ library

PID C++ library

To Do

  • Integrate the MPU-9250 into the I2C data bus lines from the mbed

Completed

Error Detection & Indication

To Do

  • Determine best solution for controlling the WS2812B RGB LED

Completed

Kicker Board

To Do

  • Measure the current from kicker board currently used
  • Update the kicker board to accommodate the new battery's voltage of 18.5V

Completed

Battery & Power

The following contains a listing of batteries that were considered for the 2015 design along with other battery/power adapters and accessories.

To Do

Completed

  • Change the first switching regulator to accomidate for the higher voltage battery
  • Finalized the new design's battery selection

Battery Accessories

All Batteries

The following list contains batteries that were considered and known about during the battery selction period. The list is not inclusive.

Phase III: Production

The final phase for creating the new fleet of robots involves outlining the steps and procedures for robot manufacturing and assebly. Future members can use this area as a reference for the fleet's required maintenance. It may also be benefitial for strengthening tolerances in future fleet builds.

Electronics Assembly

General

Solder Paste Stencil Creation

SparkFun uses SolderMask, Inc for their stencil needs

  • Laser cutting kapton film


  • Chemical etching aluminum
    • Untested but very promosing
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