Difference between revisions of "RoboCup: Redesign 2014-2015"
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| Line 52: | Line 52: | ||
*Determine optimal secondary frequency for base station updates | *Determine optimal secondary frequency for base station updates | ||
*Test methods using breakout boards and compare data rates | *Test methods using breakout boards and compare data rates | ||
| − | *Successfully communicate using two (2) | + | *Successfully communicate using two (2) [https://www.nordicsemi.com/eng/Products/2.4GHz-RF/nRF24L01P nRF24L01+] transceivers and two (2) mbeds |
*Research and determine best steps for structuring radio protocol with ''primary ''and ''seconday ''frequencies | *Research and determine best steps for structuring radio protocol with ''primary ''and ''seconday ''frequencies | ||
| + | *Research integration options of the [http://www.ti.com/product/CC1111F32?keyMatch=cc1111&tisearch=Search-EN CC1111 ]and [https://www.nordicsemi.com/eng/Products/2.4GHz-RF/nRF24LU1P nRF24LU1+] | ||
==== Completed ==== | ==== Completed ==== | ||
| − | *Successfully communicate using two (2) CC1101 transceivers and two (2) mbeds | + | *Successfully communicate using two (2) [http://www.ti.com/product/cc1101?keyMatch=cc1101&tisearch=Search-EN CC1101 ]transceivers and two (2) mbeds |
| − | *Obtain breakout boards for CC1101 and | + | *Obtain breakout boards for [http://www.ti.com/product/cc1101?keyMatch=cc1101&tisearch=Search-EN CC1101 ]and [https://www.nordicsemi.com/eng/Products/2.4GHz-RF/nRF24L01P nRF24L01+] |
=== FPGA === | === FPGA === | ||
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A few major change to the FPGA's Verilog code must be made for the 2015 redesign. This means documentation mean be produced/located for how the FPGA currently communicates on the SPI bus and append documentation for new protocol. | A few major change to the FPGA's Verilog code must be made for the 2015 redesign. This means documentation mean be produced/located for how the FPGA currently communicates on the SPI bus and append documentation for new protocol. | ||
| − | http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html | + | [http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html] |
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! scope="col" | Command | ! scope="col" | Command | ||
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! scope="col" | Array Index | ! scope="col" | Array Index | ||
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! scope="col" | Array Index | ! scope="col" | Array Index | ||
Revision as of 01:36, 7 December 2014
Contents
Phase I: Techanical Analysis
The first stage of the 2014-2015 RoboCup redesign involves brainstorming potential upgrades by researching new technologies/resources since the last revision. A parallel analysis of current robot bugs and potential enhancements is also done at this time. Outlined below is a listing of resources that the team used in it's brainstorming stage.
Competition 2014 [FINISH UPLOADING IMAGES TO THIS PAGE. MANY ARE MISSING]
Phase II: Design
Controlling Unit
To Do
Completed
- Obtain mbeds for robot use
Layout
To Do
- Determine location and placement for dribbler motor header
- Determine optimal placement direction for drive motor's phase connections (motor board)
- Add connection header for ball sensor to control board
- Add wires among connections in CAD assembly files
- Test motor wire modifications before working on the entire batch of motors
- Determine kicker connections and integration
Completed
- Update hall connection header to right angled one
- Add pin locations to all connection housings in CAD part files
- Update the 14-pin connection header (female) for the control-to-motor board connection
- Finalize method for adjusting motor wire lengths when motors arrive
- Determine placement of battery location
Radio
Current protocol [LINK TO BE CREATED & UPDATED]
To Do
- Determine optimal secondary frequency for base station updates
- Test methods using breakout boards and compare data rates
- Successfully communicate using two (2) nRF24L01+ transceivers and two (2) mbeds
- Research and determine best steps for structuring radio protocol with primary and seconday frequencies
- Research integration options of the CC1111 and nRF24LU1+
Completed
- Successfully communicate using two (2) CC1101 transceivers and two (2) mbeds
- Obtain breakout boards for CC1101 and nRF24L01+
FPGA
A few major change to the FPGA's Verilog code must be made for the 2015 redesign. This means documentation mean be produced/located for how the FPGA currently communicates on the SPI bus and append documentation for new protocol.
http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html
| Command | Read/Write | Definition |
|---|---|---|
| 0x00 | Read Only | Receive Data Readings |
| 0x01 | Write | Set motor speeds |
| Array Index | Bit(s) | Definition |
|---|---|---|
| 0 | 7..0 | FPGA Version (0x04 in 2014) |
| 1 | 7..0 | Encoder 1 Count (LSB) |
| 2 | 7..0 |
Encoder 1 Count (MSB) |
| 3 | 7..0 |
Encoder 2 Count (LSB) |
| 4 | 7..0 |
Encoder 2 Count (MSB) |
| 5 | 7..0 |
Encoder 3 Count (LSB) |
| 6 | 7..0 |
Encoder 3 Count (MSB) |
| 7 | 7..0 |
Encoder 4 Count (LSB) |
| 8 | 7..0 |
Encoder 4 Count (MSB) |
| 9 | 7..0 |
Motor Fault |
| 10 | 7..0 |
Kicker Status |
| 11 | 7..0 |
Kicker Voltage |
| 12 | 7..0 |
Hall Count 1 |
| 13 | 7..0 |
Hall Count 2 |
| 14 | 7..0 |
Hall Count 3 |
| 15 | 7..0 | Hall Count 4 |
| 16 | 7..0 |
Hall Count 5 |
| Array Index | Bit(s) | Definition |
|---|---|---|
| 0 | 7..0 | Packet Type (0x01) |
| 1 | 7..0 | Motor 1 Speed (LSB) |
| 2 | 7..4 |
Reserved (Always 0) |
| 3..2 | Motor 1 Drive Mode | |
| 1..0 | Motor 1 Speed (MSB) | |
| 3 | 7..0 | Motor 2 Speed (LSB) |
| 4 | 7..4 | Reserved (Always 0) |
| 3..2 | Motor 2 Drive Mode | |
| 1..0 | Motor 2 Speed (MSB) | |
| 5 | 7..0 | Motor 3 Speed (LSB) |
| 6 | 7..4 | Reserved (Always 0) |
| 3..2 | Motor 3 Drive Mode | |
| 1..0 | Motor 3 Speed (MSB) | |
| 7 | 7..0 | Motor 4 Speed (LSB) |
| 8 | 7..4 | Reserved (Always 0) |
| 3..2 | Motor 4 Drive Mode | |
| 0..1 | Motor 4 Speed (MSB) | |
| 9 | 7..0 | Dribbler Motor Speed (LSB) |
| 10 | 7 | Kicker Charge |
| 6 | Chipper Enable (1=Chip, 0=Kick) | |
| 5..4 | Reserved (Always 0) | |
| 3..2 | Dribbler Motor Drive Mode | |
| 1..0 | Dribbler Motor Speed (MSB) | |
| 11 | 7..0 | Kicker Power |
To Do
- Transition the I2C bus lines to the microcontroller
- Update Verilog for new balanced encoder signals (A+, A-, B+, B-)
- ( (A+) + (A-) == 0 ) should be true for no errors
Completed
- Determine what communications occur over the SPI bus
- Finalized that the 2015 motor will use the current FPGA
- Xilinx Spartan-3E
Motors
http://wiki.robojackets.org/w/File:Maxon_50W_Motor_Custom_Design.pdf
http://wiki.robojackets.org/w/File:Maxon_50W_Motor_Datasheet.pdf
To Do
- Order motor controller boards
- Test different circuits and document data result set to wiki
Completed
- Finalize the protyping designs of single motor controllers
Motion Sensing
To Do
- Integrate the MPU-9250 into the I2C data bus lines from the mbed
Completed
- Order breakout board for MPU-9250
Error Detection
To Do
- Create breakout board for MCP23017 and place on GitHub repo (robocup-pcb)
- Update EAGLE part libraries too
Completed
Battery & Power
The following contains a listing of batteries that were considered for the 2015 design along with other battery/power adapters and accessories.
Battery
Zippy Flightmax 2200mAh 5S 40C
Connector
Charging Lead
Balancing Board
All Batteries
Zippy Flightmax 2500mAh 5S 20C
Zippy Flightmax 1800mAh 5S 40C
Phase III: Production
Electronics Assembly
https://learn.sparkfun.com/tutorials/electronics-assembly
http://www.soldermask.com/ <- Sparfun uses these guys for all their solder stencils
