Difference between revisions of "RoboCup: Redesign 2014-2015"

Revision as of 17:31, 29 December 2014

Phase I: Techanical Analysis

The first stage of the 2014-2015 RoboCup redesign involves brainstorming potential upgrades by researching new technologies/resources since the last revision. A parallel analysis of current robot bugs and potential enhancements is also done at this time. Outlined below is a listing of resources that the team used in this brainstorming stage.

Competition 2014 documentation

Team Description Papers (TDP)

Electrical Board Error Logs

Past Electrical Designs

Phase II: Design

During the design phase, specifications are determined for each section of the robot. Experimental results are documented here from all quantitative findings. This phase is also where the high-level ideas from Phase I are tracked to ensure completion.

Logical Controlling Unit

mbed Debugging

To Do

Successfully communicate over SPI with a current FPGA and mbed

Completed

Build development board for testing FPGA configuration from mbed's flash storage
- Tested and confirmed working
Obtain mbeds for robot use
- How: 15 mbeds donated by ECE department

Mechanical/Electrical Integration

Max PCB Dimensions

To Do

Determine location and placement for dribbler motor header
Determine optimal placement direction for drive motor's phase connections (motor board)
Add connection header for ball sensor to control board
Add wires among connections in CAD assembly files
Test motor wire modifications before working on the entire batch of motors
Determine kicker connections and integration
Determine options using quarter-turn screws for electrical board attachment

Completed

Update hall connection header to right angled one
Add pin locations to all connection housings in CAD part files
Update the 14-pin connection header (female) for the control-to-motor board connection
Finalize method for adjusting motor wire lengths when motors arrive
- Decision: Unsolder from motor's PCB, trim to length, and resolder to motor's PCB
- Reason: Did not want to delay ordering motors any futher & hand soldering results in higher yields compared against hand crimping
Determine placement of battery location

Radio

CC1101 C++ library

nRF24L01+ C++ library

Current protocol [LINK TO BE CREATED & UPDATED]

To Do

Determine optimal secondary frequency for base station updates
Test methods using breakout boards and compare data rates
Successfully communicate using two (2) nRF24L01+ transceivers and two (2) mbeds
Research and determine best steps for structuring radio protocol with primary and seconday frequencies
- The Crazyflie project has basic radio documentation for how they implemented real-time communication with room for expansion
Test packet optimizations - Nanopb is promosing for this

Completed

Research integration options of the CC1111 and nRF24LU1+
- Decision: Do not use SoC parts for the base station
- Reason: Keep radio software on the mbed platform's C++ libraries (SoC would require additional C code for the base station)
Order five (5) CC1111 transceivers from TI
Successfully communicate using two (2) CC1101 transceivers and two (2) mbeds
Obtain breakout boards for CC1101
- How: Added SMA antenna connector to breakout boards from 2008 fleet
Obtain breakout boards for nRF24L01+
- How: eBay

FPGA

A few major change to the FPGA's Verilog code must be made for the 2015 redesign.

Setting up a computer for Verilog development

Create an account on Xilinx's website
The Xilinx program is called ISE Design Suite (this is on ECE's virtual lab pool computers - can connect to it from anywhere).
- The desired download link is found under the ISE Design Suite heading
- The current version at the time of this writing is 14.7 (size: ~6GB)
- The ISE Design Suite is no longer supported
- The newer version of Xilinx's software is called Vivado Design Tools, but it does not support the Spartan-3E FPGA
Install the program to your computer
- The installer will prompt you to select an edition to install
  - Select ISE WebPACK
Obtain a license at the Xilinx page for license management
- Open the link sent to you after requesting a license
- Navigate to the Manage Licenses tab
- Download the license called ISE WebPACK License
Save the downloaded license file to the Xilinx directory of your computer
- The program will require you to locate the license's path at first startup

Mandatory user-provided files for Verilog synthesis

Verilog files(s)
- Defines the HDL implementation
- File Extension: .v
Xilinx Constraint File
- Defines parameters for correct synthesis to the hardware (pin mappings)
- File Extension: .ucf

?FPGA Commands

Command	Read/Write	Definition
`0x00`	Read Only	Receive Data Readings
`0x01`	Read/Write	Set motor speeds

Array Index	Bit(s)	Definition
0	7..0	FPGA Version (`0x04` in 2014)
1	7..0	Encoder 1 Count (LSB)
2	7..0	Encoder 1 Count (MSB)
3	7..0	Encoder 2 Count (LSB)
4	7..0	Encoder 2 Count (MSB)
5	7..0	Encoder 3 Count (LSB)
6	7..0	Encoder 3 Count (MSB)
7	7..0	Encoder 4 Count (LSB)
8	7..0	Encoder 4 Count (MSB)
9	7..0	Motor Fault
10	7..0	Kicker Status
11	7..0	Kicker Voltage
12	7..0	Hall Count 1
13	7..0	Hall Count 2
14	7..0	Hall Count 3
15	7..0	Hall Count 4
16	7..0	Hall Count 5

Array Index	Bit(s)	Definition
0	7..0	Packet Type (`0x01`)
1	7..0	Motor 1 Speed (LSB)
2	7..4	Reserved (Always `0x00`)
	3..2	Motor 1 Drive Mode
	1..0	Motor 1 Speed (MSB)
3	7..0	Motor 2 Speed (LSB)
4	7..4	Reserved (Always `0x00`)
	3..2	Motor 2 Drive Mode
	1..0	Motor 2 Speed (MSB)
5	7..0	Motor 3 Speed (LSB)
6	7..4	Reserved (Always `0x00`)
	3..2	Motor 3 Drive Mode
	1..0	Motor 3 Speed (MSB)
7	7..0	Motor 4 Speed (LSB)
8	7..4	Reserved (Always `0x00`)
	3..2	Motor 4 Drive Mode
	0..1	Motor 4 Speed (MSB)
9	7..0	Dribbler Motor Speed (LSB)
10	7	Kicker Charge
	6	Chipper Enable (`1=Chip`, `0=Kick`)
	5..4	Reserved (Always 0)
	3..2	Dribbler Motor Drive Mode
	1..0	Dribbler Motor Speed (MSB)
11	7..0	Kicker Power (<, `oxFF=6ms`)

To Do

Transition the I²C bus lines to the microcontroller
Update Verilog for new balanced encoder signals (A+, A-, B+, B-)
- ( (A+) + (A-) == 0 ) should be true for no errors
Update Verilog for driving a bootstrap circuit
Add a writable register for enabling/disabling motor encoders

Completed

Document steps for synthesizing Verilog files
Successfully configured an FPGA from the mbed's on board flash storage
Successfully synthesized a Hello World Verilog file using Xilinx's ISE Webtools
Determine what communications occur over the SPI bus
- Documented in the tables above
Finalized that the 2015 motors will use the current FPGA
- Decision: Xilinx Spartan-3E
- Reason: FPGA is only used for motor control & no futher capabilities are needed

Motors

Maxon 50W Custom Motor Drawing

Maxon 50W Motor Datasheet

To Do

Order motor controller boards
Test different circuits and document data result set to wiki

Completed

Order 3 DRV8301 Pre-Drivers from TI
Finalize the protyping designs of single motor controllers
Order motors

Motion Sensing & Motion Control

MPU-9250 C++ library

PID C++ library

To Do

Integrate the MPU-9250 into the I²C data bus lines from the mbed

Completed

Order breakout board for MPU-9250

Error Detection & Indication

To Do

Determine best solution for controlling the WS2812B RGB LED

Completed

Order breakout board for RGB LED
Create breakout board for MCP23017 and place on GitHub repository

Kicker Board

To Do

Measure the current from kicker boards currently used
Update the kicker board to accommodate the new battery's voltage of 18.5V

Completed

Battery & Power

The following contains a listing of batteries that were considered for the 2015 design along with other battery/power adapters and accessories.

To Do

Determine power switch placement and integration

Completed

Phase III: Production

The final phase for creating the new fleet of robots involves outlining the steps and procedures for robot manufacturing and assebly. Future members can use this area as a reference for the fleet's required maintenance. It may also be benefitial for strengthening tolerances in future fleet builds.

Electronics Assembly

Solder Paste Stencil Creation

https://learn.sparkfun.com/tutorials/electronics-assembly

http://www.soldermask.com/ <- Sparfun uses these guys for all their solder stencils

Kapton film & laser cutter
- Tested and not precise enough
Chemical etching aluminum
- Untested but very promosing

@@ Line 93: / Line 93: @@
 ----
-A few major change to the FPGA's [http://en.wikipedia.org/wiki/Verilog Verilog] code must be made for the 2015 redesign. This means documentation mean be produced/located for how the FPGA currently communicates on the SPI bus and append documentation for new protocol.
+A few major change to the FPGA's [http://en.wikipedia.org/wiki/Verilog Verilog] code must be made for the 2015 redesign.
-<u>'''Setting up a computer for Verilog development'''</u>
+==== Setting up a computer for Verilog development ====
 #Create an account on [http://www.xilinx.com/ Xilinx's website]
@@ Line 102: / Line 102: @@
 #*The current version at the time of this writing is ''14.7 ''(size: ~6GB)
 #*The '''<span style="color:#FF8C00;">ISE Design Suite</span>''' is no longer supported
-#*The newer version of Xilinx's software is called [http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html Vivado Design Tools]&nbsp;and does not support the [http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf Spartan-3E] FPGA
+#*The newer version of Xilinx's software is called [http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html Vivado Design Tools], but it&nbsp;does not support the [http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf Spartan-3E] FPGA
 #Install the program to your computer
 #*The installer will prompt you to select an edition to install
 #**Select ''ISE WebPACK''
 #Obtain a license at the Xilinx page for [http://www.xilinx.com/getlicense license management]
-#*You will be an email once your license request is approved
+#*Open the link sent to you after requesting a license
-#Download the license
-#*Follow the link sent in the email
 #*Navigate to the <span style="color:#000080;">'''Manage Licenses'''</span> tab
 #*Download the license called <span style="color:#0000FF;">ISE WebPACK License</span>
-#Save the downloaded license file to the Xilinx directory of your computer
+#Save the downloaded license file to the <code>Xilinx </code>directory of your computer
-#*The program will require you to locate the license file at first startup
+#*The program will require you to locate the license's path at first startup
-<u>'''Mandatory user-provided files for Verilog synthesis'''</u>
+==== Mandatory user-provided files for Verilog synthesis ====
-*Verilog files(s)
+*[https://en.wikipedia.org/wiki/Verilog Verilog ]files(s)
 **Defines the HDL implementation
-**.v
+**File Extension: <code>.v</code>
 *[http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf Xilinx Constraint File]
 **Defines parameters for correct synthesis to the hardware (pin mappings)
-**.ucf
+**File Extension: <code>''.ucf''</code>
+<code>''?FPGA Commands''</code>
 {| class="wikitable" style="width: 500px;"
@@ Line 130: / Line 130: @@
 ! scope="col" | Definition
 |-
-| style="text-align: center;" | 0x00
+| style="text-align: center;" | <code>0x00</code>
 | style="text-align: center;" | Read Only
 | style="text-align: center;" | Receive Data Readings
 |-
-| style="text-align: center;" | 0x01
+| style="text-align: center;" | <code>0x01</code>
-| style="text-align: center;" | Write
+| style="text-align: center;" | Read/Write
 | style="text-align: center;" | Set motor speeds
 |}
@@ Line 149: / Line 149: @@
 | style="text-align: center;" | 0
 | style="text-align: center;" | 7..0
-| style="text-align: center;" | FPGA Version (0x04 in 2014)
+| style="text-align: center;" | FPGA Version (<code>0x04 </code>in 2014)
 |-
 | style="text-align: center;" | 1
@@ Line 226: / Line 226: @@
 | style="text-align: center;" | 0
 | style="text-align: center;" | 7..0
-| style="text-align: center;" | Packet Type (0x01)
+| style="text-align: center;" | Packet Type (<code>0x01</code>)
 |-
 | style="text-align: center;" | 1
@@ Line 235: / Line 235: @@
 | style="text-align: center;" | 7..4
 | style="text-align: center;" |
-<span style="line-height: 20.7999992370605px; text-align: center;">Reserved (Always 0)</span>
+<span style="line-height: 20.7999992370605px; text-align: center;">Reserved (Always <code>0x00</code>)</span>
 |-
@@ Line 250: / Line 250: @@
 | style="text-align: center;" rowspan="3" | 4
 | style="text-align: center;" | 7..4
-| style="text-align: center;" | Reserved (Always 0)
+| style="text-align: center;" | Reserved (Always <code>0x00</code>)
 |-
 | style="text-align: center;" | 3..2
@@ Line 264: / Line 264: @@
 | style="text-align: center;" rowspan="3" | 6
 | style="text-align: center;" | 7..4
-| style="text-align: center;" | <span style="line-height: 20.7999992370605px; text-align: center;">Reserved (Always 0)</span><br/>
+| style="text-align: center;" | <span style="line-height: 20.7999992370605px; text-align: center;">Reserved (Always <code>0x00</code>)</span><br/>
 |-
 | style="text-align: center;" | 3..2
@@ Line 278: / Line 278: @@
 | style="text-align: center;" rowspan="3" | 8
 | style="text-align: center;" | 7..4
-| style="text-align: center;" | Reserved (Always 0)<br/>
+| style="text-align: center;" | Reserved (Always <code>0x00</code>)<br/>
 |-
 | style="text-align: center;" | 3..2
@@ Line 295: / Line 295: @@
 |-
 | style="text-align: center;" | 6
-| style="text-align: center;" | Chipper Enable (1=Chip, 0=Kick)
+| style="text-align: center;" | Chipper Enable (<code>1=Chip</code>, <code>0=Kick</code>)
 |-
 | style="text-align: center;" | 5..4
@@ Line 308: / Line 308: @@
 | style="text-align: center;" | 11
 | style="text-align: center;" | 7..0
-| style="text-align: center;" | Kicker Power (0255=6ms)
+| style="text-align: center;" | Kicker Power (<code>0x00</code>, <code>oxFF=6ms</code>)
 |}
@@ Line 316: / Line 316: @@
 *Update Verilog for new balanced encoder signals ('''A+''', '''A-''', '''B+''', '''B-''')
 **( ''('''A+''') + ('''A-''') == 0'' ) should be true for no errors
-*Update Verilog for [https://redmine.robojackets.org/issues/355 driving a bootstrap circuit]
+*Update [https://en.wikipedia.org/wiki/Verilog Verilog] for [https://redmine.robojackets.org/issues/355 driving a bootstrap circuit]
+*Add a writable register for enabling/disabling motor encoders
 ==== Completed ====
-*Document steps for synthesizing Verilog files
+*Document steps for synthesizing [https://en.wikipedia.org/wiki/Verilog Verilog ]files
-*Successfully configured an FPGA from the mbed's on board flash storage
+*Successfully configured an FPGA from the [https://developer.mbed.org/handbook/LocalFileSystem mbed's on board flash storage]
-*Successfully synthesized a ''Hello World''&nbsp;Verilog file using Xilinx's [http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html ISE Webtools]
+*Successfully synthesized a <code>Hello World</code>&nbsp;Verilog file using Xilinx's [http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html ISE Webtools]
-*Determine what communications occur over the SPI bus
+*Determine what communications occur over the [https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus SPI] bus
 **''Documented in the tables above''
 *Finalized that the 2015 motors will use the current FPGA

Difference between revisions of "RoboCup: Redesign 2014-2015"

Revision as of 17:31, 29 December 2014

Contents

Phase I: Techanical Analysis

Phase II: Design

Logical Controlling Unit

To Do

Completed

Mechanical/Electrical Integration

To Do

Completed

Radio

To Do

Completed

FPGA

Setting up a computer for Verilog development

Mandatory user-provided files for Verilog synthesis

To Do

Completed

Motors

To Do

Completed

Motion Sensing & Motion Control

To Do

Completed

Error Detection & Indication

To Do

Completed

Kicker Board

To Do

Completed

Battery & Power

To Do

Completed

Battery

Connector

Charging Lead

Balancing Board

All Batteries

Phase III: Production

Electronics Assembly

Navigation menu

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