EAGLE Style Guide

Part Creation

Symbol

Grid

• Size: 0.1 in
• Alt: 0.01 in

Name

• Should be manufacturer part/family number (eg. ATTINY167-SU)

Description

• Leave blank

Style

• Origin
  • Center origin (crosshair) on symbol center
• Text
  • Keep text horizontal
  • Size: 0.07 in
  • Ratio: 8%
  • Line Distance: 50%
  • Font: proportional
• Name
  • Locate in top left of symbol
  • Align: bottom-left
  • Layer: 95 Names
  • Value: >NAME
• Value
  • Locate in bottom-left of symbol
  • Align: top-left
  • Layer: 96 Values
  • Value: >VALUE
• Outline
  • Use Lines
    • Width: 0.01 in
    • Style: continuous
    • Layer: 94 Symbol
    • Curve: 0
  • Try to have a length/width that is a 0.1 in multiple (eg. 0.4 in by 0.4 in)

Functionality

• Pins
  • Label pins to allow the symbol to be applied to parts in similar families
  • Name: Based on part datasheet
  • Direction: pas (passive)
  • Swap Level: 0
  • Length: middle
  • Function: none
  • Visible: both
• Pin Placement
  • Power (VCC): top left
  • Ground (GND): bottom right
  • Inputs: left edge
  • Outputs: right edge
• Passive Pins
  • Specifically resistors, capacitors, inductors, fuses, diodes
  • Visible: off
• Connector Pins
  • Try to reuse an existing symbol for the size of connector
  • If need to make a new one, for pins:
    • Visible: pad
• Decimal Labeling
  • For fractional values include the decimal point (eg. 3.3V, 4.5K)

Footprint

Grid

• Size: 1 mm
• Alt: 0.1 mm

Name

• Should be manufacturer footprint name (eg. SOIC-20)

Description

• Link to datasheet for part/family for pad layout

Style

• Origin
  • Center origin (crosshair) on footprint center
• Text
  • Keep text horizontal
  • Size: 1 mm
  • Ratio: 8%
  • Line Distance: 50%
  • Font: vector
• Name
  • Locate in top left of footprint
  • Align: bottom-left
  • Layer: 25 tNames
  • Value: >NAME
• Value
  • Locate in bottom-left of symbol
  • Align: top-left
  • Layer: 26 tValues
  • Value: >VALUE
• Outline
  • Use Lines
    • Width: 0.2 mm
    • Style: continuous
    • Layer: 21 tPlace
  • Draw package outline per part/family datasheet
  • Used for part placement
• Keepout
  • Use Rectangles
    • Layer: 39 tKeepout
  • Size 0.1 mm larger than the package
  • Used to prevent overlapping parts
• Details
  • Capture more part details, extensions beyond outline, etc
  • Use
    • Width: 0.2 mm
    • Style: continuous
    • Layer: 51 tDocu

Functionality

• Pad (Through-hole)
  • Name: name based on datasheet pin number
  • Diameter: auto
  • Drill: size based on datasheet
  • Shape: circle
  • Locked: unchecked
  • Thermals: checked
  • Stop: checked
  • First: unchecked
• Smd (Surface Mount)
  • Name: name based on datasheet pin number
  • Smd Size: size based on datasheet
  • Layer: 1 Top (usually)
  • Roundness: 0%
  • Locked: unchecked
  • Thermals: checked
  • Stop: checked
  • Cream: checked
• Polarity Indication
  • Through-hole
  • Make pin 1 visually different
    • Shape: square
  • Indicate polarity, when necessary
    • Prevents backwards installation
    • Direction or cathode indicators for diodes
    • Stripe or plus-minus for capacitors
  • Indicate Pin 1 for ICs
    • Use a circle (dot)
      • Width: 0 mm
      • Layer: 21 tPlace
      • Radius: 0.2 mm (at minimum)
  • Avoid overlapping pads with silkscreen, cut a section out

Device

Attributes

• Name should be manufacturer part number
• Attribute - DKPN should be filled with the Digi-Key part number

Descriptions

• One sentence describes the function of the part
• Datasheet link (if available)

Prefix

Chart for Designation

Letter	Part Type
A	Separable assembly or sub-assembly (e.g. printed circuit assembly)
C	Capacitor
D	Diode, LED
F	Fuse
FB	Ferrite bead
J	Jack or Connector (least moveable connection part)
JP	Jumper
K	Relay or Contactor
L	Inductor
LS/BZ	Loudspeaker or Buzzer
M	Motor
P	Plug (most moveable connection part)
PS	Power Supply
Q	Transistor
R	Resistor
RN	Resistor Network
S	Switch
T	Transformer
TP	Test Point
U	Integrated Circuit
X	Crystal

Schematics

Overall

• Organize subsystems as follows:
• Related subsystems should be grouped into a sheet
• Each subsystem in a sheet should be boxed clearly, and that box labeled
  • Use line tool, width 0.006, shortdash, layer 97 info
  • Label font
    • Font - vector
    • Ratio - 12%
    • Size - 0.25 in
    • Layer - Info
  • Every sheet should have the following:
    • A frame no bigger than 11 x 17" (8½ x 11” preferred), which should have the following info:
    • A name
    • Last edit date
    • Last edit engineer(s)
    • Schematic version
    • Page #
  • Frames within a schematic should all be the same size

Nets

• Every net should have a name if possible
  • Use xref tags at 0.05 size
• Every bus should have a name and description
• Every power net should be labeled with the acceptable voltage range and max current at the net driver
• Differentially routed nets should be commented as such as the driver and sink
• Impedance controlled nets should be commented as such as the driver and sink
• Power and Ground nets
  • Use symbol with appropriate name

Configs

• Any value computed (e.g. varies by application) from a datasheet should be noted
• Any optional parts should be noted
• 0ohm isolation resistor and 0ohm jumper resistors should be noted

Boards

Fab House / Validation

• Load fab house DRC before place and route
• RoboJackets has slightly conservative DRCs for 2 and 4 layer boards

Placement

• Keep analog electronics far from high power electronics
• Locate power net status LEDs near power sources
• Provide adequate spacing for stitching/shielding if needed
• Verify any mechanical considerations
  • Board mounting holes
  • Component mounting holes/cutouts
  • Use tDoc/bDoc and/or tKeepout/bKeepout for bolt head size to prevent traces near mounting
• Place decoupling capacitors as close to the power pin of the IC as possible
  • Smallest values should be closest to pin to minimize parasitic inductance

Routing

• Avoid minimum trace width where possible
  • Suggestions: 0.2 to 0.3mm for signals, 0.4 to 0.5mm for power (increase as needed for current rating)
• Avoid minimum trace spacing where possible
• Avoid minimum drill/via size where possible
  • Suggestions: 0.35mm drill, 0.65mm diameter for vias
• Do not split differentially routed pairs unless impedance and arrival time can be matched
• Avoid vias on signals above 1GHz
• Use the same number of vias on differentially routed traces
• For two layer boards, try to keep component, signal, and power on the top layer and ground return on the bottom layer
• High frequency signals should have continuous low impedance return path directly beneath trace.
• Keep high frequency signals isolated from other signals to minimize crosstalk
• Route signals orthogonally to avoid cross-talk

Silkscreen

• This is far more important than most people realize and can take a significant amount of time to get right. A good silkscreen makes a board easier to use, easier to debug, and harder to break.

Meta

• Have at least a "vMAJOR.minor" version label on the board
• Have your team name and year (optionally month, Ubuntu style) on the board
• Have your team logo on the board
• Have a filled white square to write in an instance ID
  • Recommended if more than three boards will be fabricated
  • e.g. can say "board #2 is broken", there is a "2" written on the white square
  • Cover ink with Kapton tape
• Don’t place them on vias (even tented vias) unless absolutely unavoidable

Components & Connectors

• Set default line width to 0.2mm
• Label all power inputs with name and voltage (current optional)
• Label all connectors with name
• Label all switches with position values
• Label all debug LEDs
• Label all fuses with current rating (type optional)

Font

• All font should be vector rendered
• All font should be ratio 8%, unless made bold for end user benefit
• Component font size should be "1"
  • e.g. R45, Q1, etc.
• Layer - t/bPlace