EAGLE Style Guide

Part Creation

Symbol

Grid

• Size: 0.1 in
• Alt: 0.01 in

Name

• Should be manufacturer part/family number (eg. ATTINY167-SU)

Description

• Leave blank

Style

• Origin
  • Center origin (crosshair) on symbol center
• Text
  • Keep text horizontal
  • Size: 0.07 in
  • Line Distance: 50%
  • Font: proportional
• Name
  • Locate in top left of symbol
  • Align: bottom-left
  • Layer: 95 Names
  • Value: >NAME
• Value
  • Locate in bottom-left of symbol
  • Align: top-left
  • Layer: 96 Values
  • Value: >VALUE
• Outline
  • Use Lines
    • Width: 0.01 in
    • Style: continuous
    • Layer: 94 Symbol
    • Curve: 0
  • Try to have a length/width that is a 0.1 in multiple (eg. 0.4 in by 0.4 in)

Functionality

• Pins
  • Label pins to allow the symbol to be applied to parts in similar families
  • Name: Based on part datasheet
  • Direction: pas (passive)
  • Swap Level: 0
  • Length: middle
  • Function: none
  • Visible: both
• Pin Placement
  • Power (VCC): top left
  • Ground (GND): bottom right
  • Inputs: left edge
  • Outputs: right edge
• Passive Pins
  • Specifically resistors, capacitors, inductors, fuses, diodes
  • Visible: off
• Connector Pins
  • Try to reuse an existing symbol for the size of connector
  • If need to make a new one, for pins:
    • Visible: pad
• Decimal Labeling
  • For fractional values include the decimal point (eg. 3.3V, 4.5K)

Footprint

Grid

• Size: 1 mm
• Alt: 0.1 mm

Name

• Should be manufacturer footprint name (eg. SOIC-20)

Description

• Link to datasheet for part/family for pad layout

Style

• Origin
  • Center origin (crosshair) on footprint center
• Text
  • Keep text horizontal
  • Size: 1 mm
  • Ratio: 10%
  • Line Distance: 50%
  • Font: vector
• Name
  • Locate in top left of footprint
  • Align: bottom-left
  • Layer: 25 tNames
  • Value: >NAME
• Value
  • Locate in bottom-left of symbol
  • Align: top-left
  • Layer: 27 tValues
  • Value: >VALUE
• Outline
  • Use Lines
    • Width: 0.2 mm
    • Style: continuous
    • Layer: 21 tPlace
  • Draw package outline per part/family datasheet
  • Used for part placement
• Keepout
  • Use Rectangles
    • Layer: 39 tKeepout
  • Size 0.1 mm larger than the package
  • Used to prevent overlapping parts
• Details
  • Capture more part details, extensions beyond outline, etc
  • Use
    • Width: 0.2 mm
    • Style: continuous
    • Layer: 51 tDocu

Functionality

• Pad (Through-hole)
  • Name: name based on datasheet pin number
  • Diameter: auto
  • Drill: size based on datasheet
  • Shape: circle
  • Locked: unchecked
  • Thermals: checked
  • Stop: checked
  • First: unchecked
• Smd (Surface Mount)
  • Name: name based on datasheet pin number
  • Smd Size: size based on datasheet
  • Layer: 1 Top (usually)
  • Roundness: 0%
  • Locked: unchecked
  • Thermals: checked
  • Stop: checked
  • Cream: checked
• Polarity Indication
  • Through-hole
    • Make pin 1 visually different
    • Shape: square
  • Indicate polarity, when necessary
    • Prevents backwards installation
    • Direction or cathode indicators for diodes
    • Stripe or plus-minus for capacitors
  • Indicate Pin 1 for ICs
    • Use a circle (dot)
      • Width: 0 mm
      • Layer: 21 tPlace
      • Radius: 0.2 mm (at minimum)
  • Avoid overlapping pads with silkscreen, cut a section out

Device

Name

• Should be manufacturer part number (eg. ATTINY167-SU)
• Wildcards
  • Allows devices with multiple technologies (specifications) or packages
    • Uses wildcards in device name
    • Technology Name: *
    • Package Name: ?
  • Example
    • Regulator with two voltage (3.3V and 1.8V) technologies
      • AP2138N-3.3TRG1 for 3.3V
      • AP2138N-1.8TRG1 for 1.8V
      • Becomes AP2138N-*TRG1 with technology 3.3 and 1.8

Description

• One sentence part function overview (valid for all variants)
• Datasheet link

Value

• Off unless its a passive part (resistors, capacitors, inductors, fuses, diodes)
• If its a specific passive part with a value, add an attribute
  • Name: VALUE
  • Value: the value
  • Type: variable

Symbol

• Use specific symbol for that part/family
• Connectors are an exception
  • Generic symbol used for all connectors of a certain size

Footprint

• Use specific footprint if unique
• Try to reuse a footprint if it matches

Attribute (non-Passives)

• Part number
  • Name: DKPN
  • Value: the Digi-Key Part Number (eg. ATTINY167-SU-ND)
  • Type: variable

Attribute (Passives)

• Part number
  • Name: DKPN
  • Value: blank unless specific to part
  • Type: variable
• Resistors
  • Should have tolerance and power ratings that is blank by default
  • Value is for resistance only
  • Tolerance
    • Name: TOL
    • Value: blank unless specific to part
    • Type: variable
  • Power
    • Name: POW
    • Value: blank unless specific to part
    • Type: variable
• Capacitors
  • Should have tolerance and voltage ratings that is blank by default
  • Value is for capacitance only
  • Tolerance
    • Name: TOL
    • Value: blank unless specific to part
    • Type: variable
  • Voltage
    • Name: VOLT
    • Value: blank unless specific to part
    • Type: variable
• Inductors
  • Should have tolerance and current ratings that is blank by default
  • Value is for inductance only
  • Tolerance
    • Name: TOL
    • Value: blank unless specific to part
    • Type: variable
  • Current
    • Name: CUR
    • Value: blank unless specific to part
    • Type: variable
• Fuses
  • Value is for current rating
• Diodes
  • LEDs
    • Value should be color
  • Normal Diode
    • Value should be reverse voltage
  • TVS Diode
    • Value should be [Working Voltage]-[Breakdown Voltage] (e.g. 8V-8.5V)

Prefix

Chart for Prefix Designators

Letter	Part Type
A	Separate Assembly or Subassembly
C	Capacitor
D	Diode or LED
F	Fuse
FB	Ferrite bead
J	Jack or Connector (least moveable connection part)
JP	Jumper
K	Relay or Contactor
L	Inductor
LS/BZ	Loudspeaker or Buzzer
M	Motor
P	Plug (most moveable connection part)
POT	Potentiometer
PS	Power Supply
Q	Transistor
R	Resistor
RN	Resistor Network
S/SW	Switch
T	Transformer
TP	Test Point
U	Integrated Circuit
X	Crystal
XF	External Fuse

Schematics

Grid

• Size: 0.1 in
• Alt: 0.01 in

Sheets

Overall

• Group related subsystems into a sheet
• Have only 1 frame per sheet

Frames

• A 11 x 17" frame with the following attributes
  • TEAM: RoboJackets team name
  • SCH_DESC: Short summary of content in the frame
  • REVISION: Schematic version
• Group related subsystems into boxes
  • Use Lines
    • Width: 0.006 in
    • Style: shortdash
    • Layer: 97 Info
    • Curve: 0
  • Label using Text
    • Size: 0.07 in
    • Ratio: 8%
    • Line Distance: 50%
    • Font: proportional
    • Align: bottom-left
    • Layer: 97 Info

Description

• Should match the SCH_DESC from the frame

Nets

Style

• Text
  • Size: 0.05 in
  • Ratio: 8%
  • Line Distance: 50%
  • Font: proportional
  • Align: bottom-left
  • Layer: 97 Info

Signals

• Should have a name if possible
• Label every net:
  • Size: 0.05
  • Ratio: 8%
  • Font: proportional
  • Align: bottom-left
  • Layer: 95 Names
  • Xref: checked

Power

• Use symbols with appropriate name as necessary
• Label with the voltage range and max current at driver
• Use Text

Busses

• Should have a name and description
• Use Text

Notes

Computed Values

• Note values derived from a datasheet with a short explanation
• Use Text within the box of the part in question

Specific Parts

• Note optional parts
• Note 0ohm isolation resistors and 0ohm jumper resistors
• Use Text within the box of the part in question

Boards

Grid

• Size: 1 mm
• Alt: 0.1 mm

Board Fab

• Load design rules before placement and routing
  • Allows spacing constraints to be known to tool
• Check this repo for common EAGLE DRC files per fab

Placement

General

• LEDs
  • Locate power status LEDs near power sources
• Noise prevention
  • Keep analog electronics far from high power electronics
  • Provide adequate spacing for via stitching/shielding if needed
• Decoupling capacitors
  • Recommended 1 per power pin on an IC
  • Place as close as possible to the power pin
  • Use multiple if necessary
    • Reduces noise
    • Place smallest value closest to the pin

Mechanical Considerations

• Plan for board mounting holes
  • Figure out size of the hole and necessary clearance
  • Prevent components and traces from being near bolt heads
• Plan for board cutouts and shape
  • Mark these before placement and routing
    • Use 51 tDoc / 52 bDoc to indicate cutout
  • Prevent components and traces from being near the cutout
• Prevent components and traces from overlapping
  • Use 39 tKeepout / 40 bKeepout to block components
  • Use 41 tKeepout / 42 bKeepout to block copper and traces

Routing

General Practices

• For two layer boards, try to keep components, signals, and power on the top layer and a ground plane on the bottom layer
  • Use Polygon
    • Width: 0.2mm
    • Cap: round
    • Layer: 16 Bottom
    • Curve: 0
    • Polygon Pour: solid
    • Spacing: 0.05
    • Isolate: 0
    • Rank: 1
    • Orphans: unchecked
    • Thermals: unchecked
• Use extra internal layers when necessary
  • Allows for simplified power routing
  • Leaves more space for signal traces
  • Put power planes internally
    • Layer 2 and 15 on 4 layer boards
    • Layer 2, 3, 14, and 15 on 6 layer boards
• Route signals orthogonally to avoid cross-talk between different layers (for boards >2 layers)
• Differential signals
  • Do not split differentially routed pairs unless impedance and arrival time can be matched
• High frequency
  • High frequency signals should have continuous low impedance return path directly beneath trace.
  • Keep high frequency signals isolated from other signals to minimize crosstalk

Traces

• In general
  • Style: continuous
  • Cap: round
  • Curve: 0
• Signals
  • Width: 0.3mm
• Power
  • Width: 0.5mm (increase as necessary for current requirements)
• Avoid minimum sizing (based on the DRC) when possible

Vias

• At minimum
  • Diameter: 0.65mm
  • Drill: 0.35mm
  • Shape: round
  • Layer: 1-16
• Avoid minimum sizing (based on the DRC) when possible
• Avoid vias on signals above 1GHz
• Use the same number of vias on differentially routed traces

Silkscreen

• Far more important than most people realize and can take a significant amount of time to get right
• Makes a board easier to use, easier to debug, and harder to break

Style

• Text
  • Size: 1 mm (at minimum)
  • Ratio: 8% (Important text can be bolded using 15%)
  • Line Distance: 50%
  • Font: vector
  • Layer: 21 tPlace / 22 bPlace
• Markings (anything not already in footprints)
  • Will be in final board output
  • Use Lines
    • Width: 0.2 mm
    • Style: continuous
    • Layer: 21 tPlace / 22 bPlace
• Extra Details
  • Will not be in final board output
  • Capture more details, extensions beyond outline, etc
  • Use Lines
    • Width: 0.2 mm
    • Style: continuous
    • Layer: 51 tDocu / 52 bDocu
• Measurements
  • Will not be in final board output
  • Useful to mark critical distances
  • Can mark outer board dimensions
  • Use Dimension
    • Size: 2 mm
    • Ratio: 8% (Important dimensions can be bolded using 15%)
    • Layer: 47 Measures
    • DType: parallel
    • Line Width: 0.2mm
    • Ext. Line Width:v auto
    • Ext. Line Length: auto
    • Ext. Line Offset: auto
    • Unit: mm
    • Precision: 3
    • Show unit: checked

Labels

• Label all power inputs with name and voltage (current optional)
• Label all connectors with name
• Label all switches with position values (e.g. on or off)
• Label all debug LEDs (e.g. MCU Status)
• Label all fuses with current rating

General

• Aesthetics
  • Don’t place silkscreen on vias (even tented vias) unless absolutely unavoidable
  • Have your team logo on the board (e.g. RoboBuzz)
• Versioning
  • Have a "vMAJOR.minor" version text label on the board (e.g. v2.1)
  • Have your team name and year on the board (e.g. RoboCup 2020)
• Board ID
  • White square to allow for a board ID (e.g. written 2 means board 2)
  • Recommended if more than three boards will be fabricated
  • Use Rectangle
    • Make width and height 5mm by 5mm (minimum)
    • Layer: 21 tPlace / 22 bPlace